library ieee;
use ieee.std_logic_1164.all;

entity memory is
	port( AluOutM, WriteDataM : in std_logic_vector(31 downto 0);
		   ZeroM, MemWrite, BranchM, clk, dump : in std_logic;
		   ReadDataM : out std_logic_vector(31 downto 0);
		   PCSrcM : out std_logic);
end entity;

architecture memory_arch of memory is

	component dmem
  	port(clk, we: in std_logic;
		  a, wd: in std_logic_vector(31 downto 0);
		  rd: out std_logic_vector(31 downto 0);
		  dump: in std_logic);
	end component;
	
	component signext is
	port ( a : in std_logic_vector(15 downto 0);
		    y : out std_logic_vector(31 downto 0));
	end component;
	
	signal aux, aux2 : std_logic_vector(31 downto 0);
	
	begin
		aux <= x"0000" & AluOutM(31 downto 16);
		aux2 <= x"0000" & WriteDataM(31 downto 16);
	
		dmem_M: dmem port map (a => aux, wd => aux2, clk=>clk, we=>MemWrite, rd=>ReadDataM, dump=>dump);
		PCSrcM <= BranchM and ZeroM;

end architecture;
